Instruction and logic for a logical move in an out-of-order processor

A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.