Reprogram without erase using capacity in multi-level NAND cells

Inventive aspects include a memory device having one or more memory pages including a plurality of memory cells each having a plurality of programmable state levels. The memory device includes a memory control logic section including a program logic section and page-level reprogram state metadata. The program logic section may program the plurality of memory cells dependent on the page-level reprogram state metadata. The program logic section may program a first state level, a second state level, and a third state level of each of the memory cells in consecutive programming operations of the plurality of memory cells dependent on the page-level reprogram state metadata, without requiring any erase operations or read operations during or between the programming operations. Any combination of 1's bit, 2's bit, 4's bit, 8's bit, or 2(N−1)'s bit locations can be written to in a single program operation, as long as the lower order bits are not re-used for later writes, and proper state keeping is kept.