Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flow

Various mechanisms identify an electronic design model and determine a data propagation diagram by receiving a set of path property sources or destinations, determine a set of helper properties for the data propagation diagram by traversing at least a portion of the data propagation diagram, and verify the electronic design model by examining one or more helper properties and determining verification of the one or more helper properties leads to concrete results to generate verification results. Data propagation diagrams may be annotated with verification results to show verification progresses, highlight sources of complexity, and be further synchronized with waveform displays of one or more traces. Search space may be trimmed during a verification flow to enhance performance of verification engine(s). New start states closer to the final state than the default state may be identified during verification and used to enhance performance of the verification engine.