Low latency scheduling on simultaneous multi-threading cores

Low latency scheduling on simultaneous multi-threading cores

A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further include...

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Hauptverfasser: Warrier Suresh E, Mealey Bruce
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Warrier Suresh E
Mealey Bruce
description A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9817696B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9817696B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9817696B23</originalsourceid><addsrcrecordid>eNrjZLDxyS9XyEksSc1LrlQoTs5ITSnNycxLV8jPUyjOzC3NKUnMS80vLVYAMTN1SzKKUhNTQPLJ-UWpxTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JD402NLC0NzM0szJyJgIJQDRgDBJ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Low latency scheduling on simultaneous multi-threading cores</title><source>esp@cenet</source><creator>Warrier Suresh E ; Mealey Bruce</creator><creatorcontrib>Warrier Suresh E ; Mealey Bruce</creatorcontrib><description>A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20171114&amp;DB=EPODOC&amp;CC=US&amp;NR=9817696B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20171114&amp;DB=EPODOC&amp;CC=US&amp;NR=9817696B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Warrier Suresh E</creatorcontrib><creatorcontrib>Mealey Bruce</creatorcontrib><title>Low latency scheduling on simultaneous multi-threading cores</title><description>A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDxyS9XyEksSc1LrlQoTs5ITSnNycxLV8jPUyjOzC3NKUnMS80vLVYAMTN1SzKKUhNTQPLJ-UWpxTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JD402NLC0NzM0szJyJgIJQDRgDBJ</recordid><startdate>20171114</startdate><enddate>20171114</enddate><creator>Warrier Suresh E</creator><creator>Mealey Bruce</creator><scope>EVB</scope></search><sort><creationdate>20171114</creationdate><title>Low latency scheduling on simultaneous multi-threading cores</title><author>Warrier Suresh E ; Mealey Bruce</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9817696B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Warrier Suresh E</creatorcontrib><creatorcontrib>Mealey Bruce</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Warrier Suresh E</au><au>Mealey Bruce</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Low latency scheduling on simultaneous multi-threading cores</title><date>2017-11-14</date><risdate>2017</risdate><abstract>A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Low latency scheduling on simultaneous multi-threading cores
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T10%3A48%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Warrier%20Suresh%20E&rft.date=2017-11-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9817696B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true