Flag non-modification extension for ISA instructions using prefixes

In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of th...

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Bibliographische Detailangaben
Hauptverfasser: Combs Jonathan D, Brandt Jason W, Valentine Robert
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.