Secure memory repartitioning

Secure memory repartitioning

Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages that are convertible to secure pages or non-secu...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Neiger Gilbert, Shanbhogue Vedvyas, Chhabra Siddhartha, Scarlata Vincent R, Makaram Raghunandan, McKeen Francis X, Goldsmith Michael A, Leslie-Hurd Rebekah M, Rozas Carlos V, Santoni Amy L, Savagaonkar Uday R, Anati Ittai, Alexandrovich Ilya, Johnson Simon P, Smith Wesley H
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section that is convertible in response to a section conversion instruction.