Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads

A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator tes...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Rimon Michal, Morimoto Yugi, Mullen Michael P, Hendrickson Olaf K
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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