Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads

Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads

A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator tes...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Rimon Michal, Morimoto Yugi, Mullen Michael P, Hendrickson Olaf K
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.