Voltage follower circuit to mitigate gain loss caused by finite output impedance of transistors

Voltage follower circuit to mitigate gain loss caused by finite output impedance of transistors

Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Subraya Anantha Melavarige, Mahadev Naveen, Khasnis Himamshu Gopalakrishna
Format: Patent
Sprache:eng
Schlagworte:
AMPLIFIERS
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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Beschreibung
Zusammenfassung:Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-Channel JFET voltage replica generation circuit and a PNP BJT voltage replica generation circuit. The overall gain for the various transistor families is almost equal to unity.