Separate N and P fin etching for reduced CMOS device leakage

Separate N and P fin etching for reduced CMOS device leakage

A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fi...

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Bibliographische Detailangaben
Hauptverfasser: Karve Gauri, Seshadri Indira P, Ebrish Mona A, Priyadarshini Deepika, Saulnier Nicole A, Clevenger Lawrence A, Clevenger Leigh Anne H, Lie Fee Li, Chu Isabel C
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.