Package substrate and semiconductor package including the same

A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kim Young-Deuk, Choi Mi-Na, Hwang Hee-Jung, Jang Eon-Soo, Kim Jae-Choon
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.