Phase locked loop system with bandwidth measurement and calibration

A phase locked loop (PLL) system includes a PLL and a calibration circuit. The PLL has a reference clock input, a voltage controlled oscillator (VCO) clock output, and a feedback clock output. The calibration circuit provides a reference clock signal to the reference clock input of the PLL, induces...

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Bibliographische Detailangaben
Hauptverfasser:	Fischette, Jr. Dennis, Ang Boon-Aik, Chiang Meei-Ling
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	A phase locked loop (PLL) system includes a PLL and a calibration circuit. The PLL has a reference clock input, a voltage controlled oscillator (VCO) clock output, and a feedback clock output. The calibration circuit provides a reference clock signal to the reference clock input of the PLL, induces first and second phase disturbances between the reference clock signal and a feedback clock signal, measures respective first and second zero crossing times of a phase error between the reference clock signal and the feedback clock signal, and estimates a bandwidth of the PLL in response to an average of the first and second zero crossing times.