Three-dimensional P-I-N memory device and method reading thereof using hole current detection

A p-i-n junction structure is formed within a memory film laterally surrounded by an alternating plurality of electrically insulating layers and electrically conductive layers to provide a three-dimensional memory structure. The p-i-n junction includes a lower junction between an intrinsic semicondu...

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Bibliographische Detailangaben
1. Verfasser: Sakakibara Kiyohiko
Format: Patent
Sprache:eng
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Zusammenfassung:A p-i-n junction structure is formed within a memory film laterally surrounded by an alternating plurality of electrically insulating layers and electrically conductive layers to provide a three-dimensional memory structure. The p-i-n junction includes a lower junction between an intrinsic semiconductor channel portion and a lower doped semiconductor portion and an upper junction between the intrinsic semiconductor channel portion and an upper doped semiconductor portion. The memory film can be subsequently formed on a sidewall of the memory opening, and the intrinsic semiconductor channel portion can be deposited on the memory opening and the lower doped semiconductor portion. The upper doped semiconductor portion can be formed above a topmost electrically conductive layer. The lower doped semiconductor portion can provide hole charge carriers for electrical current.