Highly scalable single-poly non-volatile memory cell

A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the s...

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Bibliographische Detailangaben
Hauptverfasser:	Li Chun-Hsiao, Chen Hsuen-Wei, Hsu Te-Hsun
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES STATIC STORES
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Beschreibung
Zusammenfassung:	A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.