Methodology to achieve zero warpage for IC package

Methodology to achieve zero warpage for IC package

A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness.

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Bibliographische Detailangaben
Hauptverfasser: Hsu Jun Chung, Zhao Jie-Hua
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness.