On chip characterization of timing parameters for memory ports

A circuit and method for memory characterization. The circuit includes first and second programmable delay lines, address and data registers, an output register and a finite state machine controller. The finite state machine controller supplies an address to the address register, data to the data register and controlling a delay of the first programmable delay line and the second programmable delay line in at least one predetermined sequence to determine an operating characteristic of the memory to be tested. The programmable delay lines may be connected as a ring oscillator. Determination of the frequency of the ring oscillator via a counter determines the delay of the delay line. The programmable delay lines, the address register and data registers, the output register, the finite state machine controller and the memory to be tested are preferably constructed on a same semiconductor substrate.