Template matching for resilience and security characteristics of sub-component chip designs

A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.