DRAM with SDRAM interface, and hybrid flash memory module
When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory modu...
Gespeichert in:
Hauptverfasser: | , , , , , , , , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Osaka Hideki Sumikura Taishi Shibata Masabumi Fukumura Yuusuke Idei Akio Fukuda Yuichi Muraoka Satoshi Uematsu Yutaka Ueno Hitoshi Watanabe Satoru Kakita Hiroshi Naito Michinori Ono Takayuki Miyagawa Takashi |
description | When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9569144B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9569144B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9569144B23</originalsourceid><addsrcrecordid>eNrjZLB0CXL0VSjPLMlQCAYzM_NKUovSEpNTdRQS81IUMiqTijJTFNJyEoszFHJTc_OLKhVy81NKc1J5GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcQHQiLzUkvjQYEtTM0tDExMnI2MilAAALFgtFA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DRAM with SDRAM interface, and hybrid flash memory module</title><source>esp@cenet</source><creator>Osaka Hideki ; Sumikura Taishi ; Shibata Masabumi ; Fukumura Yuusuke ; Idei Akio ; Fukuda Yuichi ; Muraoka Satoshi ; Uematsu Yutaka ; Ueno Hitoshi ; Watanabe Satoru ; Kakita Hiroshi ; Naito Michinori ; Ono Takayuki ; Miyagawa Takashi</creator><creatorcontrib>Osaka Hideki ; Sumikura Taishi ; Shibata Masabumi ; Fukumura Yuusuke ; Idei Akio ; Fukuda Yuichi ; Muraoka Satoshi ; Uematsu Yutaka ; Ueno Hitoshi ; Watanabe Satoru ; Kakita Hiroshi ; Naito Michinori ; Ono Takayuki ; Miyagawa Takashi</creatorcontrib><description>When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170214&DB=EPODOC&CC=US&NR=9569144B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170214&DB=EPODOC&CC=US&NR=9569144B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Osaka Hideki</creatorcontrib><creatorcontrib>Sumikura Taishi</creatorcontrib><creatorcontrib>Shibata Masabumi</creatorcontrib><creatorcontrib>Fukumura Yuusuke</creatorcontrib><creatorcontrib>Idei Akio</creatorcontrib><creatorcontrib>Fukuda Yuichi</creatorcontrib><creatorcontrib>Muraoka Satoshi</creatorcontrib><creatorcontrib>Uematsu Yutaka</creatorcontrib><creatorcontrib>Ueno Hitoshi</creatorcontrib><creatorcontrib>Watanabe Satoru</creatorcontrib><creatorcontrib>Kakita Hiroshi</creatorcontrib><creatorcontrib>Naito Michinori</creatorcontrib><creatorcontrib>Ono Takayuki</creatorcontrib><creatorcontrib>Miyagawa Takashi</creatorcontrib><title>DRAM with SDRAM interface, and hybrid flash memory module</title><description>When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB0CXL0VSjPLMlQCAYzM_NKUovSEpNTdRQS81IUMiqTijJTFNJyEoszFHJTc_OLKhVy81NKc1J5GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcQHQiLzUkvjQYEtTM0tDExMnI2MilAAALFgtFA</recordid><startdate>20170214</startdate><enddate>20170214</enddate><creator>Osaka Hideki</creator><creator>Sumikura Taishi</creator><creator>Shibata Masabumi</creator><creator>Fukumura Yuusuke</creator><creator>Idei Akio</creator><creator>Fukuda Yuichi</creator><creator>Muraoka Satoshi</creator><creator>Uematsu Yutaka</creator><creator>Ueno Hitoshi</creator><creator>Watanabe Satoru</creator><creator>Kakita Hiroshi</creator><creator>Naito Michinori</creator><creator>Ono Takayuki</creator><creator>Miyagawa Takashi</creator><scope>EVB</scope></search><sort><creationdate>20170214</creationdate><title>DRAM with SDRAM interface, and hybrid flash memory module</title><author>Osaka Hideki ; Sumikura Taishi ; Shibata Masabumi ; Fukumura Yuusuke ; Idei Akio ; Fukuda Yuichi ; Muraoka Satoshi ; Uematsu Yutaka ; Ueno Hitoshi ; Watanabe Satoru ; Kakita Hiroshi ; Naito Michinori ; Ono Takayuki ; Miyagawa Takashi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9569144B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Osaka Hideki</creatorcontrib><creatorcontrib>Sumikura Taishi</creatorcontrib><creatorcontrib>Shibata Masabumi</creatorcontrib><creatorcontrib>Fukumura Yuusuke</creatorcontrib><creatorcontrib>Idei Akio</creatorcontrib><creatorcontrib>Fukuda Yuichi</creatorcontrib><creatorcontrib>Muraoka Satoshi</creatorcontrib><creatorcontrib>Uematsu Yutaka</creatorcontrib><creatorcontrib>Ueno Hitoshi</creatorcontrib><creatorcontrib>Watanabe Satoru</creatorcontrib><creatorcontrib>Kakita Hiroshi</creatorcontrib><creatorcontrib>Naito Michinori</creatorcontrib><creatorcontrib>Ono Takayuki</creatorcontrib><creatorcontrib>Miyagawa Takashi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Osaka Hideki</au><au>Sumikura Taishi</au><au>Shibata Masabumi</au><au>Fukumura Yuusuke</au><au>Idei Akio</au><au>Fukuda Yuichi</au><au>Muraoka Satoshi</au><au>Uematsu Yutaka</au><au>Ueno Hitoshi</au><au>Watanabe Satoru</au><au>Kakita Hiroshi</au><au>Naito Michinori</au><au>Ono Takayuki</au><au>Miyagawa Takashi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DRAM with SDRAM interface, and hybrid flash memory module</title><date>2017-02-14</date><risdate>2017</risdate><abstract>When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US9569144B2 |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
title | DRAM with SDRAM interface, and hybrid flash memory module |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T17%3A17%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Osaka%20Hideki&rft.date=2017-02-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9569144B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |