Semiconductor device and process

Semiconductor device and process

A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the co...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Lin Tien-Lu, Wang Yung-Chih, Liao Yu-Chieh, Kao Hsiang-Lun
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Lin Tien-Lu
Wang Yung-Chih
Liao Yu-Chieh
Kao Hsiang-Lun
description A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9564396B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9564396B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9564396B23</originalsourceid><addsrcrecordid>eNrjZFAITs3NTM7PSylNLskvUkhJLctMTlVIzEtRKCjKT04tLuZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwZamZibGlmZORsZEKAEAJsIlTg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device and process</title><source>esp@cenet</source><creator>Lin Tien-Lu ; Wang Yung-Chih ; Liao Yu-Chieh ; Kao Hsiang-Lun</creator><creatorcontrib>Lin Tien-Lu ; Wang Yung-Chih ; Liao Yu-Chieh ; Kao Hsiang-Lun</creatorcontrib><description>A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170207&amp;DB=EPODOC&amp;CC=US&amp;NR=9564396B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170207&amp;DB=EPODOC&amp;CC=US&amp;NR=9564396B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lin Tien-Lu</creatorcontrib><creatorcontrib>Wang Yung-Chih</creatorcontrib><creatorcontrib>Liao Yu-Chieh</creatorcontrib><creatorcontrib>Kao Hsiang-Lun</creatorcontrib><title>Semiconductor device and process</title><description>A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAITs3NTM7PSylNLskvUkhJLctMTlVIzEtRKCjKT04tLuZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwZamZibGlmZORsZEKAEAJsIlTg</recordid><startdate>20170207</startdate><enddate>20170207</enddate><creator>Lin Tien-Lu</creator><creator>Wang Yung-Chih</creator><creator>Liao Yu-Chieh</creator><creator>Kao Hsiang-Lun</creator><scope>EVB</scope></search><sort><creationdate>20170207</creationdate><title>Semiconductor device and process</title><author>Lin Tien-Lu ; Wang Yung-Chih ; Liao Yu-Chieh ; Kao Hsiang-Lun</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9564396B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lin Tien-Lu</creatorcontrib><creatorcontrib>Wang Yung-Chih</creatorcontrib><creatorcontrib>Liao Yu-Chieh</creatorcontrib><creatorcontrib>Kao Hsiang-Lun</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lin Tien-Lu</au><au>Wang Yung-Chih</au><au>Liao Yu-Chieh</au><au>Kao Hsiang-Lun</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device and process</title><date>2017-02-07</date><risdate>2017</risdate><abstract>A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US9564396B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor device and process
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T11%3A12%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lin%20Tien-Lu&rft.date=2017-02-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS9564396B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true