System on chip with debug controller and operating method thereof

A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first multiplexer and a second multiplexer. The first UART controller and the second UART controller have different baud rates. The UART port has a R×D pin coupled to a R×D pin of the second UART controller. The debug controller generates a control signal with a first state and checks whether a received data from the UART controller is equal to a keyword after power-up or a hardware reset. When the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.