Time-interleaved analog-to-digital converter

A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1/N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N−1) variable delay circuit that adjusts delay time for at least (N−1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N−1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.