Clock and data recovery circuit

A clock and data recovery (CDR) circuit that receives an input signal and generates clock and sampled output signals includes a phase-frequency detector (PFD) circuit, a control circuit, a digital-to-analog converter (DAC), a current-controlled oscillator (CCO) and a data sampler. The PFD generates intermediate and fine digital control signals. The DAC receives the intermediate digital control signal as a coarse digital control signal and the fine digital control signal and generates an output current. The CCO receives the output current and generates the clock signal. The coarse digital control signal is used to coarse calibrate a frequency of the clock signal and the fine digital control signal is used to fine calibrate the frequency of the clock signal. The data sampler receives the clock signal and samples the input signal at the frequency of the clock signal to generate the sampled output signal.