Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support

Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support

Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.

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Bibliographische Detailangaben
Hauptverfasser: Yang Bo, Sanghani Amit, Nataraj Sagar, Natarajan Karthikeyan
Format: Patent
Sprache:eng
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.