Lower receiving pin arrangement method and lower receiving pin return method

A pre-array temporary placement area A2 and a post-return temporary placement area A3 are set along with a lower receiving area A1. Temporary placement positions TP for lower receiving pins 22 in the pre-array temporary placement area A2 and the post-return temporary placement area A3 are previously...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Morishima Mie, Yamashita Shirou, Endo Tadashi, Kitashima Hironori, Matsumura Hiroshi
Format:	Patent
Sprache:	eng
Schlagworte:	CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A pre-array temporary placement area A2 and a post-return temporary placement area A3 are set along with a lower receiving area A1. Temporary placement positions TP for lower receiving pins 22 in the pre-array temporary placement area A2 and the post-return temporary placement area A3 are previously assigned in consideration of requirements for preventing occurrence of interference between the lower receiving pins 22, which would otherwise occur during transfer of the lower receiving pins 22, and in accordance with array positions AP of the lower receiving pins 22 in the lower receiving area A1. Further, a transfer sequence is set in accordance with array positions AP.