Methods for balancing write operations of SLC blocks in different memory areas and apparatus implementing the same
Data is received at a computer memory to be programmed in single-level-cell mode. A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory...
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creator | Lieber Opher |
description | Data is received at a computer memory to be programmed in single-level-cell mode. A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory are compared to determine which one of the first and second sections is a less stressed single-level-cell mode section of the computer memory. The data received at the computer memory is programmed in the less stressed single-level-cell mode section of the computer memory. |
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A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory are compared to determine which one of the first and second sections is a less stressed single-level-cell mode section of the computer memory. The data received at the computer memory is programmed in the less stressed single-level-cell mode section of the computer memory.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161115&DB=EPODOC&CC=US&NR=9495101B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161115&DB=EPODOC&CC=US&NR=9495101B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lieber Opher</creatorcontrib><title>Methods for balancing write operations of SLC blocks in different memory areas and apparatus implementing the same</title><description>Data is received at a computer memory to be programmed in single-level-cell mode. A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory are compared to determine which one of the first and second sections is a less stressed single-level-cell mode section of the computer memory. The data received at the computer memory is programmed in the less stressed single-level-cell mode section of the computer memory.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzDsOwjAQhOE0FAi4w14AifAo0hKBKKAK1NEmGRML22vZRojbYyQOQDXNN_-0CBekUYZISgJ1bNj12t3pFXQCiUfgpMVFEkXNuabOSP-IpB0NWikEuEQWVsKbOIAjsRuIvef8e2ZnvYHN6NtMIyiyxbyYKDYRi9_OCjoervVpCS8touceDqm9NdW22pWrcr_e_EE-RgRDqg</recordid><startdate>20161115</startdate><enddate>20161115</enddate><creator>Lieber Opher</creator><scope>EVB</scope></search><sort><creationdate>20161115</creationdate><title>Methods for balancing write operations of SLC blocks in different memory areas and apparatus implementing the same</title><author>Lieber Opher</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9495101B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lieber Opher</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lieber Opher</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Methods for balancing write operations of SLC blocks in different memory areas and apparatus implementing the same</title><date>2016-11-15</date><risdate>2016</risdate><abstract>Data is received at a computer memory to be programmed in single-level-cell mode. A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory are compared to determine which one of the first and second sections is a less stressed single-level-cell mode section of the computer memory. The data received at the computer memory is programmed in the less stressed single-level-cell mode section of the computer memory.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
title | Methods for balancing write operations of SLC blocks in different memory areas and apparatus implementing the same |
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