Methods for balancing write operations of SLC blocks in different memory areas and apparatus implementing the same
Data is received at a computer memory to be programmed in single-level-cell mode. A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory...
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| Zusammenfassung: | Data is received at a computer memory to be programmed in single-level-cell mode. A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory are compared to determine which one of the first and second sections is a less stressed single-level-cell mode section of the computer memory. The data received at the computer memory is programmed in the less stressed single-level-cell mode section of the computer memory. |
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