Method for decomposing a hardware model and for accelerating formal verification of the hardware model

Described is a method performed by a computing device, the method comprises: deriving a hierarchal structure of hardware instances of a hardware block, wherein the hardware block is described in a register transfer language (RTL); determining complexity of at least one hardware instance, in the hierarchal structure, with reference to a complexity metric; identifying, in response to the determined complexity of the at least one hardware instance, whether the at least one hardware instance is to be modeled; and modifying the hierarchal structure with information about the to be modeled hardware instance.