Distributed clock synchronization

A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a secon...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Huang Xuhao, Tseng Yi-Hung, Clovis Philip Michael, Chilukuri Sushma
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.