Thin film transistor substrate and the method thereof
A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line...
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| creator | Jeong Yu-Gwang Song Jean-Ho Suh Nam-Seok Kim Sung-Ryul Oh Hwa-Yeul Kim Shi-Yul Kim Jong-In Kim Byeong-Beom Hong Pil-Soon Choung Jong-Hyun Bae Yang-Ho Kim Bong-Kyun Yang Dong-Ju Choi Shin-Il Hong Sun-Young Youn Jae-Hyoung Seo O-Sung Park Je-Hyeong Lee Ki-Yeup |
| description | A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US9443881B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US9443881B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US9443881B23</originalsourceid><addsrcrecordid>eNrjZDANycjMU0jLzMlVKClKzCvOLC7JL1IoLk0qBnJLUhUS81IUSjJSFXJTSzLywcyi1Pw0HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsaWJibGFh6GRkTIQSACj9LSs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Thin film transistor substrate and the method thereof</title><source>esp@cenet</source><creator>Jeong Yu-Gwang ; Song Jean-Ho ; Suh Nam-Seok ; Kim Sung-Ryul ; Oh Hwa-Yeul ; Kim Shi-Yul ; Kim Jong-In ; Kim Byeong-Beom ; Hong Pil-Soon ; Choung Jong-Hyun ; Bae Yang-Ho ; Kim Bong-Kyun ; Yang Dong-Ju ; Choi Shin-Il ; Hong Sun-Young ; Youn Jae-Hyoung ; Seo O-Sung ; Park Je-Hyeong ; Lee Ki-Yeup</creator><creatorcontrib>Jeong Yu-Gwang ; Song Jean-Ho ; Suh Nam-Seok ; Kim Sung-Ryul ; Oh Hwa-Yeul ; Kim Shi-Yul ; Kim Jong-In ; Kim Byeong-Beom ; Hong Pil-Soon ; Choung Jong-Hyun ; Bae Yang-Ho ; Kim Bong-Kyun ; Yang Dong-Ju ; Choi Shin-Il ; Hong Sun-Young ; Youn Jae-Hyoung ; Seo O-Sung ; Park Je-Hyeong ; Lee Ki-Yeup</creatorcontrib><description>A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160913&DB=EPODOC&CC=US&NR=9443881B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160913&DB=EPODOC&CC=US&NR=9443881B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Jeong Yu-Gwang</creatorcontrib><creatorcontrib>Song Jean-Ho</creatorcontrib><creatorcontrib>Suh Nam-Seok</creatorcontrib><creatorcontrib>Kim Sung-Ryul</creatorcontrib><creatorcontrib>Oh Hwa-Yeul</creatorcontrib><creatorcontrib>Kim Shi-Yul</creatorcontrib><creatorcontrib>Kim Jong-In</creatorcontrib><creatorcontrib>Kim Byeong-Beom</creatorcontrib><creatorcontrib>Hong Pil-Soon</creatorcontrib><creatorcontrib>Choung Jong-Hyun</creatorcontrib><creatorcontrib>Bae Yang-Ho</creatorcontrib><creatorcontrib>Kim Bong-Kyun</creatorcontrib><creatorcontrib>Yang Dong-Ju</creatorcontrib><creatorcontrib>Choi Shin-Il</creatorcontrib><creatorcontrib>Hong Sun-Young</creatorcontrib><creatorcontrib>Youn Jae-Hyoung</creatorcontrib><creatorcontrib>Seo O-Sung</creatorcontrib><creatorcontrib>Park Je-Hyeong</creatorcontrib><creatorcontrib>Lee Ki-Yeup</creatorcontrib><title>Thin film transistor substrate and the method thereof</title><description>A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDANycjMU0jLzMlVKClKzCvOLC7JL1IoLk0qBnJLUhUS81IUSjJSFXJTSzLywcyi1Pw0HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsaWJibGFh6GRkTIQSACj9LSs</recordid><startdate>20160913</startdate><enddate>20160913</enddate><creator>Jeong Yu-Gwang</creator><creator>Song Jean-Ho</creator><creator>Suh Nam-Seok</creator><creator>Kim Sung-Ryul</creator><creator>Oh Hwa-Yeul</creator><creator>Kim Shi-Yul</creator><creator>Kim Jong-In</creator><creator>Kim Byeong-Beom</creator><creator>Hong Pil-Soon</creator><creator>Choung Jong-Hyun</creator><creator>Bae Yang-Ho</creator><creator>Kim Bong-Kyun</creator><creator>Yang Dong-Ju</creator><creator>Choi Shin-Il</creator><creator>Hong Sun-Young</creator><creator>Youn Jae-Hyoung</creator><creator>Seo O-Sung</creator><creator>Park Je-Hyeong</creator><creator>Lee Ki-Yeup</creator><scope>EVB</scope></search><sort><creationdate>20160913</creationdate><title>Thin film transistor substrate and the method thereof</title><author>Jeong Yu-Gwang ; Song Jean-Ho ; Suh Nam-Seok ; Kim Sung-Ryul ; Oh Hwa-Yeul ; Kim Shi-Yul ; Kim Jong-In ; Kim Byeong-Beom ; Hong Pil-Soon ; Choung Jong-Hyun ; Bae Yang-Ho ; Kim Bong-Kyun ; Yang Dong-Ju ; Choi Shin-Il ; Hong Sun-Young ; Youn Jae-Hyoung ; Seo O-Sung ; Park Je-Hyeong ; Lee Ki-Yeup</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9443881B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Jeong Yu-Gwang</creatorcontrib><creatorcontrib>Song Jean-Ho</creatorcontrib><creatorcontrib>Suh Nam-Seok</creatorcontrib><creatorcontrib>Kim Sung-Ryul</creatorcontrib><creatorcontrib>Oh Hwa-Yeul</creatorcontrib><creatorcontrib>Kim Shi-Yul</creatorcontrib><creatorcontrib>Kim Jong-In</creatorcontrib><creatorcontrib>Kim Byeong-Beom</creatorcontrib><creatorcontrib>Hong Pil-Soon</creatorcontrib><creatorcontrib>Choung Jong-Hyun</creatorcontrib><creatorcontrib>Bae Yang-Ho</creatorcontrib><creatorcontrib>Kim Bong-Kyun</creatorcontrib><creatorcontrib>Yang Dong-Ju</creatorcontrib><creatorcontrib>Choi Shin-Il</creatorcontrib><creatorcontrib>Hong Sun-Young</creatorcontrib><creatorcontrib>Youn Jae-Hyoung</creatorcontrib><creatorcontrib>Seo O-Sung</creatorcontrib><creatorcontrib>Park Je-Hyeong</creatorcontrib><creatorcontrib>Lee Ki-Yeup</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jeong Yu-Gwang</au><au>Song Jean-Ho</au><au>Suh Nam-Seok</au><au>Kim Sung-Ryul</au><au>Oh Hwa-Yeul</au><au>Kim Shi-Yul</au><au>Kim Jong-In</au><au>Kim Byeong-Beom</au><au>Hong Pil-Soon</au><au>Choung Jong-Hyun</au><au>Bae Yang-Ho</au><au>Kim Bong-Kyun</au><au>Yang Dong-Ju</au><au>Choi Shin-Il</au><au>Hong Sun-Young</au><au>Youn Jae-Hyoung</au><au>Seo O-Sung</au><au>Park Je-Hyeong</au><au>Lee Ki-Yeup</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Thin film transistor substrate and the method thereof</title><date>2016-09-13</date><risdate>2016</risdate><abstract>A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Thin film transistor substrate and the method thereof |
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