Mixing of low speed and high speed clocks to improve test precision of a digital integrated circuit

Implementations of the present disclosure involve an apparatus and/or method for mixing high speed and low speed clock signals during structural testing of a digital integrated circuit to improve the test precision and efficiency. In particular, the apparatus and/or method allow for a testing device to perform stuck-bit testing of the circuit by releasing one or more clock cycles of a low speed clock signal. Further, without having to reset the testing of the circuit, at-speed testing of the circuit may be conducted by the testing device. In one embodiment, at-speed testing occurs by activating a mode signal associated with the circuit design that instructs one or more clock cycles from an internal clock signal to the circuit to be released. The testing device may return to stuck-bit testing at a low speed clock signal, or continue with at-speed testing using the high speed internal clock signal.