Multi-core processor for managing data packets in communication network

A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively.