Thyristor memory and methods of operation

Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.