Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements

A processor includes a first register with first, second, third, and fourth data elements. A second register to hold fifth, sixth, seventh, and eighth data elements, and a third register. A decoder to decode a packed instruction to identify the first and second registers as source registers and the...

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Bibliographische Detailangaben

Hauptverfasser:	MENNEMEIER LARRY M, MITTAL MILLIND, YAARI YAAKOV, PELEG ALEXANDER D, EITAN BENNY
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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