Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements

A processor includes a first register with first, second, third, and fourth data elements. A second register to hold fifth, sixth, seventh, and eighth data elements, and a third register. A decoder to decode a packed instruction to identify the first and second registers as source registers and the third register as a destination register. And to decode a pack instruction to identify a fourth and a fifth register each having 16-bit data elements. At least one functional unit, responsive to the packed instruction, to store a result in the third register including only half of all data elements of each of the first and second registers, including only corresponding data elements from corresponding positions in the first and second registers, and responsive to the pack instruction to store a result that is to include an 8-bit data element for each 16-bit data element in the fourth and fifth registers.