Reading and writing to NAND flash memories using charge constrained codes

Reading and writing to NAND flash memories using charge constrained codes

A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BELLORADO JASON, SUBRAMANIAN ARUNKUMAR, LEE FREDERICK K. H, TANG XIANGYU, ZENG LINGQI
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.