Identifying layout pattern candidates
A method, system or computer usable program product for automatically identifying layout pattern candidates in selected regions for use in analyzing semiconductor device performance issues including identifying a set of target regions and a set of reference regions from a design layout; utilizing a...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | A method, system or computer usable program product for automatically identifying layout pattern candidates in selected regions for use in analyzing semiconductor device performance issues including identifying a set of target regions and a set of reference regions from a design layout; utilizing a processor to generate a reference baseline of layout patterns from the set of reference regions; utilizing the processor to compare a frequency profile of layout patterns in the set of target regions to a frequency profile of layout patterns in the reference baseline; and based on the comparison, utilizing the processor to identify candidate layout patterns from the set of target regions for further analysis. |
|---|