Deterministic clock crossing

Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die g...

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Hauptverfasser:	KULICK STANLEY STEVE, BESSETTE JASON, FRANCOM ERIN
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
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Beschreibung
Zusammenfassung:	Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.