Half-integer frequency dividers that support 50% duty cycle signal generation

A fractional-N frequency divider includes a half-integer frequency divider and a duty cycle adjustment circuit. The half-integer frequency divider includes a multi-modulus divider containing a cascaded chain of div2/3 cells, which is responsive to a multi-bit modulus control signal, and a phase control circuit configured support half-integer frequency division by the multi-modulus divider, by providing an input terminal of the multi-modulus divider with a periodically phase-flipped input signal having a first frequency. The duty-cycle adjustment circuit is configured to generate a divider output signal with a 50% duty cycle in response to a periodic signal generated by the half-integer frequency divider.