Shared logic for multiple registers with asynchronous initialization

Shared logic for multiple registers with asynchronous initialization

A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input.

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Bibliographische Detailangaben
Hauptverfasser: GUNARATNA SENANI, YEW TING, SHARPE-GEISLER BRAD
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input.