Reducing source contact to gate spacing to decrease transistor pitch

Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	LEE WINSTON, WEI CHIENUAN, WU ALBERT, SUTARDJA PANTAS, CHANG RUNZI, LEE PETER
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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