Bi-level dry etching scheme for transistor contacts

Contact holes of different depths for source, drain, and gate connections are formed by common etch steps using a relatively low etch rate material over the gate electrode and a relatively high etch rate material over the source and drain terminals to provide similar etch times for all three holes s...

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Bibliographische Detailangaben
Hauptverfasser: NOGUCHI MASATO, KUMAMOTO KEITA
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Contact holes of different depths for source, drain, and gate connections are formed by common etch steps using a relatively low etch rate material over the gate electrode and a relatively high etch rate material over the source and drain terminals to provide similar etch times for all three holes so that risk of over-etching is reduced.