Self-reset asynchronous pulse frequency modulated DROIC with extended counting and having reduced quantization noise

The present invention proposes a CMOS sensor pixel with a pulse frequency modulated digital readout integrated circuit (DROIC) comprising a photon sensitive element for receiving a plurality of photons and providing a charge signal indicative of the received photons, an integration capacitor connected to said photon sensitive element for determining a cumulative signal based on the charge signal for a certain integration time and producing an integrator output signal based on the cumulative signal and a comparator connected to the integrator for producing a comparator output signal. Each of said pixels further comprises a DAC that switches at each clock cycle following the end of an integration time and two counters respectively counting number of resets of said integration capacitor and voltage difference between an integrator output residue signal and a reference voltage of said comparator.