Burst length control circuit

A burst length control circuit includes a burst length input circuit that outputs a mode register burst length signal and a burst length on-the-fly signal, a burst length generator circuit that outputs a burst length signal, and a burst length adjuster that delays the burst length signal by a write latency time to produce a write burst length control signal. A selection circuit selects any one of the burst length signal and the write burst length control signal according to a write read command signal and an on-the-fly signal received from the burst length input circuit, and outputs a burst length control signal. A burst stop counter counts the burst length control signal according to an internal write command signal and an internal read command signal, and outputs a burst stop signal corresponding to a selected burst length.