Low power architectures

Systems and methods for operating transistors near or in the sub-threshold region to reduce power consumption are described herein. In one embodiment, a method for low power operation comprises sending a clock signal to a flop via a clock path comprising a plurality of transistors, wherein the clock signal has a high state corresponding to a high voltage that is above threshold voltages of the transistors in the clock path. The method also comprises sending a data signal to the flop via a data path comprising a plurality of transistors, wherein the data signal has a high state corresponding to a low voltage that is below threshold voltages of the transistors in the data path. The method further comprises latching the data signal at the flop using the clock signal.