FPGA-based high-speed low-latency floating point accumulator and implementation method therefor

This invention discloses a FPGA based high-speed low-latency floating-point accumulation and its implementation method. Floating accumulation of this invention comprises a floating-point adder unit, numerous intermediate result buffers, an input control unit and an output control unit. The floating-point accumulation implementation method of this invention is used for gradation of the whole accumulation calculation process to ensure cross execution of accumulation calculation processes and graded storage of intermediate results of accumulation calculation at different levels; meanwhile, the operation in the mode of pure flow line can significantly improve utilization rate of internal floating-point adder, and maintain relatively low latency to output of final results of floating-point accumulation calculation. This invention is expected to improve utilization rate of floating-point adder through dynamic allocation of input data in internal floating-point adder unit, and thereby maintains higher arithmetic speed and relatively low latency while ensuring minimized consumption of logic or DSP resources as required.