Link clock change during veritcal blanking

Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up...

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Bibliographische Detailangaben
Hauptverfasser: JOORDENS GEERTJAN, KIM MOON JUNG, WHITBY-STREVENS COLIN, TRIPATHI BRIJESH, THIARA RAMAN S
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.