Adaptive rate control of 10GBASE-T data transport system
A 10GBASE-T circuit is disclosed. The circuit includes a physical (PHY) integrated circuit and a media access control (MAC) integrated circuit. The PHY couples to a data transfer medium and carries out data transfers at a PHY data rate. The MAC integrated circuit controls access to the date transfer...
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creator | DALMIA KAMAL |
description | A 10GBASE-T circuit is disclosed. The circuit includes a physical (PHY) integrated circuit and a media access control (MAC) integrated circuit. The PHY couples to a data transfer medium and carries out data transfers at a PHY data rate. The MAC integrated circuit controls access to the date transfer medium and couples to the PHY via a bidirectional link operating at a MAC data rate. Rate control logic detects the PHY data rate, and adjusts the MAC data rate to the PHY data rate. Changes to the PHY and MAC data rates may be made at rates higher than 1 Gbps. |
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The PHY couples to a data transfer medium and carries out data transfers at a PHY data rate. The MAC integrated circuit controls access to the date transfer medium and couples to the PHY via a bidirectional link operating at a MAC data rate. Rate control logic detects the PHY data rate, and adjusts the MAC data rate to the PHY data rate. Changes to the PHY and MAC data rates may be made at rates higher than 1 Gbps.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150908&DB=EPODOC&CC=US&NR=9130695B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150908&DB=EPODOC&CC=US&NR=9130695B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DALMIA KAMAL</creatorcontrib><title>Adaptive rate control of 10GBASE-T data transport system</title><description>A 10GBASE-T circuit is disclosed. The circuit includes a physical (PHY) integrated circuit and a media access control (MAC) integrated circuit. The PHY couples to a data transfer medium and carries out data transfers at a PHY data rate. The MAC integrated circuit controls access to the date transfer medium and couples to the PHY via a bidirectional link operating at a MAC data rate. Rate control logic detects the PHY data rate, and adjusts the MAC data rate to the PHY data rate. Changes to the PHY and MAC data rates may be made at rates higher than 1 Gbps.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBwTEksKMksS1UoSixJVUjOzyspys9RyE9TMDRwd3IMdtUNUUhJLElUKClKzCsuyC8qUSiuLC5JzeVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwZaGxgZmlqZOhsZEKAEAKYos8Q</recordid><startdate>20150908</startdate><enddate>20150908</enddate><creator>DALMIA KAMAL</creator><scope>EVB</scope></search><sort><creationdate>20150908</creationdate><title>Adaptive rate control of 10GBASE-T data transport system</title><author>DALMIA KAMAL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US9130695B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>DALMIA KAMAL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DALMIA KAMAL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Adaptive rate control of 10GBASE-T data transport system</title><date>2015-09-08</date><risdate>2015</risdate><abstract>A 10GBASE-T circuit is disclosed. The circuit includes a physical (PHY) integrated circuit and a media access control (MAC) integrated circuit. The PHY couples to a data transfer medium and carries out data transfers at a PHY data rate. The MAC integrated circuit controls access to the date transfer medium and couples to the PHY via a bidirectional link operating at a MAC data rate. Rate control logic detects the PHY data rate, and adjusts the MAC data rate to the PHY data rate. Changes to the PHY and MAC data rates may be made at rates higher than 1 Gbps.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | Adaptive rate control of 10GBASE-T data transport system |
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