Biasing split gate memory cell during power-off mode

Biasing split gate memory cell during power-off mode

A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array,...

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Bibliographische Detailangaben
Hauptverfasser: GASQUET HORACIO P, HONG CHEONG MIN, SYZDEK RONALD J
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array, applies a voltage to the control gates and power to the peripheral circuitry during the standby mode, and applies an off-mode voltage to the control gates and removes power from the NVM peripheral circuitry during the off mode.