Selective area heating for 3D chip stack

A method of forming a 3D package including joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat, a first selective non-uniform cooling, and first uniform pressure, joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure, heating the 3D package and the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where a temperature of the first and second selective non-uniform heat is less than the reflow temperature of the first and second pluralities of solder bumps, respectively.