Method and structure for encapsulation and interconnection of transistors

A semiconductor device comprises one or more transistors and two or more layers of dielectric material encapsulating a front side of said one or more transistors. The gate of each of said one or more transistors is located within a cavity, or air-box, in at least one of the dielectric layers, so that the gate terminal is physically separated from said dielectric material. Such an arrangement may reduce parasitic capacitance. In another arrangement, a semiconductor device comprises one or more gallium nitride high electron mobility transistors and one or more dielectric layers encapsulating a front side of said one or more transistors, wherein the gate terminal of each of said one or more transistors is located within a cavity in at least one of the one or more dielectric layers, separated from said dielectric material.